Time: 9:15-10:00，Oct.26, 2023，Thursday

Speaker:

    Prof.Gilles Jacquemod

Université Côte d’Azur, France

Abstract:

Although Moore's Law reaches its limits, it has never applied to analog and RF circuits. From 22nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. Thanks to FDSOI technology, the access to UTBB (Ultra Thin Body and Box) transistor Back-Gates offers an extended control of the threshold voltages of the transistors, opening new opportunities to exciting performances and designing new topologies. Using complementary logic and the back-gate auto-biasing of these UTBB FDSOI transistors, we propose an efficient solution to produce novel structures of VCRO (Voltage-Controlled Ring Oscillator, which is known to address aggressively the size and power consumption reduction). This new complementary structure based on a pair of back-gate cross-coupled inverters offering a fully symmetrical operation of complementary signals, in order to reduce the phase noise. Based on this ring oscillator, a CDR (Clock and Data Recovery) is implemented. Finally, a new current mirror topology is proposed and allows us to reduce the SCE and DIBL effects and to create a negative resistor in order to realize an LC tank oscillator which offers different values between phase noise and power consumption.

Bio:

Gilles Jacquemod graduated from ICPI (CPE) Lyon, and received MSc degree (DEA) in microelectronics from Ecole Centrale Lyon in 1986. He received the Ph.D. degree in integrated electronics from INSA Lyon, in 1989. From 1990 to 2000, he worked at LEOM, Ecole Centrale Lyon, as an Associate Professor, on analog integrated circuit design and behavioral modeling of mixed domain systems. In 2000, he joined the LEAT laboratory and the Ecole Polytechnique of Nice-Sophia Antipolis (Côte d’Azur University) as full professor. Since 2011, he is head of Polytech’Lab (UPR UCA 7498). His primary research interests include analog integrated circuit design and behavioral modeling of mixed domain systems. He is also involved in RF design applied to wireless communication, and in advanced technology. He is author and co-author of more than 250 journal and conference papers, and holds 4 patents. IEEE member, he has organized a lot of international conferences. He is visiting professor at Tianjin University in China since 2014, given 30h lectures on analog CMOS design. In 2015, he was awarded “Chevalier de l’Ordre National du Mérite” by the French Minister of Higher Education and Research.